Story by Tom Baring and Jenn Wagaman
The Arctic Region Supercomputing Center is pleased to announce
that its unique hosting of a Cray SX-6 will continue through June
2004. The SX-6 will remain available to researchers in the wider
U.S. high performance computing community and, of course, to ARSC
users for benchmarking and testing.
Installed at ARSC in June 2002 as one of the first
NEC-technology supercomputers in the U.S., this system is part
of a cooperative
effort between ARSC and Cray Inc. to provide the architecture to
the wider community for testing and evaluation. The Cray SX-6 is
essentially the same technology as one node of the Japanese Earth
Simulator. Interest in the SX-6 as a point of comparison is expected
to remain strong. Examples of work done on the SX-6 by outside
researchers include:
Harvey Wasserman and Darren Kerbyson of Los
Alamos National Laboratory (LANL) used the SX-6 to measure
single-CPU performance of LANL
codes. With these data for input to their analytical model of
application scalability, they obtained what they believe is
a realistic prediction
of the performance they could expect on the Earth Simulator.
This work was presented at the Cray User Group meeting in May
2003.
Ben Cole of Sandia National Laboratory ran benchmarks for a paper
he co-authored on the projected performance of ASCI Red Storm
(currently under construction by Cray Inc.) versus the Earth
Simulator.
Celso Mendes extended support for University
of Illinois Urbana Champaign’s “SvPablo” suite
of scalable performance tools to the SX-6, using the SX-6
at
ARSC. Several other users
have benchmarked codes on the SX-6 to assess their codes’ vector
potential prior to availability of the X1.
ARSC staff have also been working on the SX-6. In
particular, Kate Hedstrom, Tom Logan, Andrew Lee, Jim Long, Guy
Robinson, Ed Kornkven
and Tom Baring have ported and benchmarked several user codes.
Robinson and Baring have presented technical papers on the SX-6
at the spring High Performance Computing Modernization Program
(HPCMP) User Conference and Cray User Group meetings, respectively.
A copy of Baring’s paper is available on ARSC’s web
site at: http://www.arsc.edu/support/technical.html.
The SX-6 CPU is a single-chip, 500Mhz 8-way vector processor with
8 vector registers of length 256, peak theoretical performance
of 8 GFLOPS and peak memory-to-CPU bandwidth of 32 GB per second.
The system located at ARSC is a single, 8-way node with 64 GB symmetric
shared memory and peak system memory bandwidth of 256 GB per second,
which balances the overall peak theoretical performance of 64 GFLOPS.
For more information about the SX-6, see http://www.arsc.edu/support/news/SX_6update2.html [link removed]
ARSC is delighted to extend its invitation to test the system for
another year, but
the clock is ticking. 
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