ARSC Training

Understanding Memory Caches

Where and When

  • date: March 27, 2009
  • time: 2:00-4:00 pm
  • location: WRRB 009

Description

In modern microprocessors, including the Opterons in Midnight and Pingo, effective use of the memory hierarchy, including the processor caches, is a critical performance factor. Although conceptually invisible to the programmer, one can in fact program toward good cache performance. Those programming techniques will be covered in the Cray Optimization workshop. This class will lay a foundational understanding of cache memory and Opteron caches in particular as preparation for the Cray training.

Instructor(s)

Ed Kornkven

Ed is an ARSC HPC Specialist

Registration

Registration is not required.
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