ARSC High-Performance Reconfigurable Computing Workshop

August 22-24, 2005

The Arctic Region Supercomputing Center (ARSC)

University of Alaska Fairbanks

Reconfigurable High-Performance Computing Systems based on conventional processors and Field Programmable Gate Arrays (FPGA) reconfigurable processors have been gaining attention. These synergistic systems have the potential of exploiting coarse-grain functional parallelism through conventional parallel processing as well as fine-grain parallelism through direct hardware execution. Many of such systems have recently been developed by major high-performance computing and reconfigurable computing vendors. For the HPCMO and DoD High-Performance Computing centers, this raises a number of questions:

1. What is the real technology readiness level given the applications of interest? 2. What are the sustained capabilities of such machines and how do they compare to conventional high-performance computers? 3. Which DoD applications can benefit from hardware reconfiguration and hardware execution? 4. What are the main considerations for a technology insertion plan?

This symposium provided a forum for leaders and application developers from the high-performance reconfigurable computing industry, university, and DoD, to address these questions through a series of talks by pioneers in this field. The talks were followed by open discussions. The symposium addressed these questions from the perspectives of applications, programmability, operating systems, architectures, and tools.

Speakers included:

Dr. Gordon Brebner, Distinguished Engineer, Xilinx Kurt Dobson, Director of Engineering, Starbridge Systems Tarek El-Ghazawi, George Washington University Jon Huppenthal, President and CEO, SRC Stefan Möhl, Mitrion Dr. Walid Najjar, Professor, University of California Riverside Dr. Greg Newby, Acting Chief Scientist, ARSC Dr. Viktor Prasanna, Professor, Universiy of Southern California Virginia Ross, Program Manager of Information Technology Division, Rome Air Force Research Lab Kevin L. Wohlever, Field Director, Ohio Supercomputer Center

The workshop spanned August 22 and August 23 and was followed by a hands-on tutorial workshop on August 24.


Day 1: Monday, August 22
Butrovich Bldg, Room 109

  • 8:00-8:30 Breakfast and Registration

Opening Session

Session I: HPRC Architectures

Session II: Panel 1 -- Architectures Issues in HPRC

  • 2:45-4:00 Panelists: Gordon, Greg, Jon, Ron, Kurt. Moderator: Tarek El-Ghazawi

Session III: Applications and Algorithms I

Day 2: Tuesday, August 23
Butrovich Bldg, Room 109

  • 8:00-8:30 Breakfast and Registration

Session III cont: Applications and Algorithms

Session IV: Programming and Tools

Session V: Panel 2 -- Programming and Application Development

  • 1:30-3:00 Stefan Mohl, Walid Najjar, David Pointer, Daniel Chavarria. Moderator: Greg Newby
  • 3:00-4:00 Open Discussion and Wrap Up
  • 4:00-5:00 Discovery Lab Tour

Day 3: Wednesday, August 24
ARSC Training Center -- West Ridge Research Building, Room W009

  • 9:00-4:00 XD1 Hands On Tutorial. Offered by Cray and hosted by ARSC

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